Carbon nanotubes outperform silicon transistors in the same size

The basic way of IC development is to develop chips with more powerful performance, higher integration and more complex functions on the premise of transistor size reduction At present, the mainstream CMOS (complementary metal oxide semiconductor) technology will reach the technical node of 10 nm (nano), and it is difficult to continue to improve due to the limitations of physical laws and manufacturing costs in the future, "Moore's law" may face the end For more than 20 years, the scientific and industrial circles have been exploring the transistor technology of various new materials and new principles in order to replace the silicon-based CMOS technology However, up to now, no new 10 nm CMOS device has been realized, and no new device can truly surpass the best silicon-based CMOS device in performance Carbon nanotubes are considered to be the ideal materials for constructing sub 10 nm transistors The diameter of carbon nanotubes at the atomic level ensures that the device has excellent grid electrostatic control ability and is easier to overcome the short channel effect; the ultra-high carrier mobility ensures that the device has higher performance and lower power consumption Theoretical research shows that compared with silicon-based devices, carbon tube devices have 5-10 times advantages in speed and power consumption, which is expected to meet the development needs of "post Moore era" integrated circuits However, in 2014, the minimum carbon tube CMOS device implemented by IBM stagnated at 20 nm gate length, and its performance was far lower than expected Professor Peng Lianmao Zhang Zhiyong, School of information science and technology, Peking University and Key Laboratory of the Ministry of education of nano device physics and chemistry, has studied in the field of carbon nanotube electronics for more than ten years, developed a set of undoped preparation methods of high-performance carbon nanotube CMOS transistors, and controlled the polarity of transistors by controlling the electrode work function In recent years, by optimizing the device structure and fabrication process, the research group has realized the first time the top gate CMOS FET with gate length of 10 nm (corresponding to 5 nm technology node), and the subthreshold swing of p-type and n-type devices is 70 MV / dec (DEC represents octave); the device performance is not only far more than all the published carbon devices, but also at a lower working voltage (0.4 5) The performance of the lower p-type and N-type transistors is better than that of the best silicon-based CMOS devices at 0.7 V (Intel's 14 nm nodes); in particular, the intrinsic gate delay of the carbon based CMOS transistors is only 0.062 PS, equivalent to 1 / 3 of the 14 nm silicon-based CMOS devices (0.22 PS) Then, the research group further explored the 5 nm gate length (corresponding to the 3 nm technology node) of the carbon tube, and used graphene as the source drain contact of the carbon tube transistor, which effectively inhibited the short channel effect and the source drain direct tunneling, so as to prepare a 5 nm gate length high-performance carbon tube transistor The device sub threshold swing reached 73 MV / Dec On this basis, the research group compares the advantages and performance potential of carbon tube CMOS devices The results show that compared with silicon-based CMOS devices with the same gate length, carbon tube CMOS devices have the comprehensive advantages of about 10 times of speed and dynamic power consumption (energy consumption delay product) and better reducibility It can be seen from the analysis of the experimental data that only about one electron is involved in the switch conversion of the 5 nm gate length carbon tube device, and the gate delay reaches 42 FS, which is very close to the limit (40 FS) of the binary electronic switch device, which is determined by the Heisenberg uncertainty principle and the Shannon von Neumann Landau law; that is to say, 5 Nm gate length carbon transistor is close to the physical limit of electronic switch At the same time, the research group also studied the influence of contact size reduction on the device performance, explored the overall size reduction of the device, reduced the contact electrode length of the carbon tube device to 25 nm, realized the carbon tube transistor with the overall size of 60 nm on the premise of ensuring the device performance, and successfully demonstrated the overall length of 240 nm Nm carbon tube CMOS inverter, which is the smallest nano inverter circuit realized at present 5 nm gate long carbon transistor (A transmission electron micrograph of cross section of carbon transistor with metal contact, scanning electron micrograph of carbon transistor with graphene as contact, B schematic diagram of carbon transistor with graphene as contact, transfer curve of C and 5 nm gate long carbon transistor) Comparison between carbon tube CMOS devices and traditional semiconductor devices (A schematic diagram of field effect transistor based on carbon tube array, B-D, comparison between carbon tube CMOS devices and traditional material transistors) This work was published online in science: 10.1126/science.aaj1628 on January 20, 2017 Qiu Chenguang, postdoctoral student of the school of information, is the first author, and Zhang Zhiyong and Peng Lianmao are co correspondents The research results not only show that the carbon nanotube CMOS devices have obvious advantages over the silicon-based CMOS devices at the technical nodes below 10 nm, but also are expected to reach the performance limit of binary electronic switch determined by uncertainty principle and thermodynamics law, which shows the great potential of carbon nanotube electronics, and provides an important reference for the development and selection of integrated circuit technology after 2020 The above research has been supported by national key R & D plan, major scientific research plan, National Natural Science Foundation (Excellent Youth Science Fund, innovative research group), Beijing Science and technology plan, Peking University "Central University Building World-class University (discipline) and characteristic development guidance project".