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    Home > Biochemistry News > Biotechnology News > The research group of Academician Huang Ru and Associate Professor Ye Le of the School of Integrated Circuits has achieved 2 important research results in the field of "ultra-low power AIoT chips"

    The research group of Academician Huang Ru and Associate Professor Ye Le of the School of Integrated Circuits has achieved 2 important research results in the field of "ultra-low power AIoT chips"

    • Last Update: 2022-04-21
    • Source: Internet
    • Author: User
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    Recently, the 69th International Solid-State Circuits Conference (ISSCC), known as the "International Olympics of Integrated Circuits" in the industry, was held online.


    1.


    For intelligent IoT application scenarios, the research group proposes a clockless asynchronous spiking neural network (SNN) architecture and circuit topology to solve the problem of low energy efficiency in AI processing caused by the separation of synchronous clock and storage and computing, using a spiking neural network with natural event triggering characteristics Replacing the traditional artificial neural network, it can achieve lightweight AI inference processing at the cost of ultra-low power consumption and ultra-low latency while achieving inference accuracy comparable to ANN; this innovation makes the chip activity and external event activity highly active Matching improves computing energy efficiency; and removes the synchronous clock network, thereby eliminating the main source of power consumption in the standby state of the chip


    Based on the above innovative technologies, the research group has developed and implemented an asynchronous pulse neural network processing chip.


    This work is based on "82nW, 0.


    Figure 1.


    2.


    For the application of AIoT chips in the smart Internet of Things, aiming at the static leakage problem of neural network weight data storage in the "real-time standby" state, an ultra-low leakage SRAM memory architecture and circuit topology are proposed, which achieves the international lowest leakage level while taking into account high-speed reading and writing.


    Based on the above innovative technologies, the research group has developed and implemented two ultra-low leakage SRAM memory chips with different standard CMOS processes


    This work is based on "Single-Mode 6T CMOS SRAM Macros with Keeper-Loading Single-Mode 2.


    Figure 2.


    ISSCC meeting background introduction:

    The ISSCC conference is held in San Francisco, USA in mid-February every year.


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