ASML’s Q1 revenue missed expectations, and nearly half of its lithography machine revenue came from China—how should we interpret this?

This situation may be quite intriguing. Let’s break it down. First, when analyzing ASML’s financial performance, we typically focus on sales revenue and new order intake. Revenue is tied to deliveries: only shipped systems count toward revenue; signed orders do not. ASML’s performance surged last year, with sales reaching €27.6 billion (including €5.6 billion from maintenance services for legacy equipment), compared to €21.2 billion in 2022 (including €5.7 billion from legacy maintenance). Excluding legacy maintenance revenue, ASML’s 2023 sales grew by 42% year-on-year. Performance strengthened progressively through the year, with Q4 achieving a record high. Who contributed most to this growth? China. A large share of the incremental deliveries in 2023 were destined for Chinese customers. Why? Because the U.S.’s new export restrictions took effect on January 1, 2024—prohibiting exports of immersion lithography systems at or above the NXT:2000i class to China, and restricting exports of NXT:1970i and NXT:1980i systems to certain Chinese entities. Thus, all parties tacitly accelerated deliveries. Although standard lead times for fulfilled orders are typically over one year, exceptional efforts were made in 2023 to ship as much as possible before the deadline. China’s procurement value from ASML in December 2023 surged tenfold year-on-year. Yet behind this impressive 2023 revenue figure lies a sharp decline in new orders. In 2022, ASML booked €30.7 billion in new orders (while its annual revenue was only €21.2 billion). In contrast, despite its strong 2023 revenue growth, new orders dropped to just €20 billion.

Domestic wafer-level packaging materials are still catching up, while panel-level packaging interposer materials have taken the lead.

Core Technical Advantages (Intel, TSMC, Samsung, Huawei, SKC) 1. Exceptional dimensional stability: Coefficient of Thermal Expansion (CTE) closely matches that of silicon wafers, enabling fabrication of ultra-large substrates with ultra-fine circuit patterns; long-term substrate flatness control solves warpage issues inherent to organic ABF substrates; 2. Ultra-low dielectric constant: Significantly reduces high-speed signal transmission delay and crosstalk, precisely controls trace impedance, and meets interconnect requirements for AI chips operating at 48 Gbps and beyond; 3. Outstanding thermal stability: Maintains dimensional integrity under wide temperature fluctuations and repeated reflow soldering cycles, substantially improving overall performance stability in multi-die stacked packages; 4. Enables five key upgrades at the packaging architecture level: finer line patterning, continuously shrinking bump pitch, higher die integration per package, ultra-high-speed signal transmission, and optimized power delivery networks. Intel has already completed physical validation using glass substrates measuring 515 mm × 510 mm. Key Industrialization Challenges 1. Brittleness-related processing and metallization reliability: Glass’s high brittleness complicates precision drilling, wiring, and metal plating adhesion; its CTE is far lower than conventional organic ABF materials, making interfacial stress-induced delamination and cracking highly likely in heterogeneous packaging stacks; poor compatibility with existing ABF processes; 2. Manufacturing and warpage control for large-area substrates: Uniform formation of ultra-large glass substrates (300–600 mm and beyond) is extremely difficult; warpage after lamination and thin-film deposition remains hard to control; 3. Triple bottlenecks—process maturity, cost, and supply chain: Full-scale mass-production processes remain immature; grinding, drilling, and laser processing yields for glass substrates are low; per-substrate manufacturing costs significantly exceed those of organic substrates; although the global ecosystem—including full sets of equipment, consumables, and processing capabilities—is now largely established, mainland China ranks among the world’s top tier. (II) Thermal Interface Materials (TIM): Critical for heat dissipation in lidless, high-performance chip packaging Application Scenarios Targeting GPU architectures without integrated heat spreaders (IHS) or lids—i.e., direct cooling of bare dies—vertical-aligned carbon fiber/carbon nanotube (ACNT)-based TIMs address the critical thermal contact resistance bottleneck between AI chips and heatsinks. The theoretical thermal conductivity of individual carbon nanotubes exceeds 2,000 W/m·K; commercially available ACNT-based TIMs achieve 10–200 W/m·K. Core Technical Bottlenecks 1. Trade-off between high thermal conductivity and interface compatibility: Blending high-conductivity fillers—such as AlN, BN, silver powder, diamond, and carbon nanotubes—at high loading ratios drastically increases paste viscosity, severely complicating dispensing and coating processes; interfacial thermal contact resistance cannot be consistently minimized; 2. Long-term reliability degradation: Organic TIMs suffer from pump-out effects, high-temperature drying/aging, and interfacial delamination; liquid Ga-In-Sn alloy TIMs corrode chip pads and metallic substrates, and exhibit inconsistent wetting behavior; 3. Process integration barriers: Surface modification of carbon-based nanomaterials is challenging; integration with substrate and chip interface engineering is complex; sintered silver or copper TIMs require high-temperature curing (>200°C) or special atmospheres (e.g., nitrogen or vacuum), demanding costly production-line upgrades; 4. Environmental compliance constraints: Liquid metals and heavy-metal fillers face strict global regulatory restrictions under RoHS and REACH directives, limiting their mass-production adoption.

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