In-depth Foreign Publication Reading | WSJ: Chipmaker Sought by Apple Soars on IPO, Becomes Most Valuable Company Listed on China’s Domestic Stock Market

The company, founded just a decade ago, sported a market capitalization equivalent to $484 billion after its opening day of trading in Shanghai, topping Industrial and Commercial Bank of China to become the most valuable company listed in a mainland Chinese market. CXMT’s market value was just short of China-based internet company Tencent, which is listed in Hong Kong and is the most valuable company in that market. CXMT is China’s national champion in the fast-growing business for memory chips dominated until now by three companies: SK Hynix and Samsung of South Korea and Micron Technology of the U.S. Prices of dynamic random-access memory, or DRAM, have skyrocketed owing to high demand from artificial-intelligence companies. With chips in short supply, manufacturers are raising prices on everything from iPhones and computers to cars.

What is the core idea behind Huawei’s proposed 'Tao Law' in chip development, and what does it mean for China’s semiconductor industry?

First, the conclusion: It is neither ‘leapfrogging via an alternative path’ nor a ‘reluctant compromise’. Rather, it marks China’s first championship win in the global race for advanced semiconductor packaging. And the value of the Tao (τ) Law surpasses that of any single chip—because it redefines the fundamental rules of the race itself. I. First, clarify what ‘logic folding’ actually is. Many people are drawn to the figure ‘1.4-nanometer equivalent’, but this number itself is not the key. The crucial point lies in how this number is achieved. Traditional chip performance improvements rely on a one-dimensional approach: lithography machines shrink transistor sizes—from 7 nanometers to 5 nanometers, then to 3 nanometers. Each shrink enables more transistors to be packed onto the same chip area, thereby naturally boosting performance. But this path has reached its end. Below 10 nanometers, quantum tunneling effects cause gate control over transistors to collapse—electrons no longer stay confined within the channel but instead ‘ghost’ through barriers, triggering a sharp surge in leakage current. This is the engineering ‘physical limit’—not a matter of whether we *want* to shrink further, but one dictated by immutable physical laws. Huawei’s logic folding, by contrast, represents a three-dimensional pathway: Step 1: Shift the core logic circuitry from a planar, single-layer layout to a vertically stacked dual-layer configuration—hence the name ‘LogicFolding’. Step 2: Replace conventional microbump interconnects with hybrid bonding—copper pads on two dies are directly pressed together at the molecular level, shrinking inter-die connection pitch from the 25-micrometer range down to 10 micrometers or less. Step 3: Deploy the SkyClock cross-die clock-synchronization scheme—to resolve clock skew between upper and lower die layers under varying operating voltages and temperatures (e.g., FF corner / SS corner). This is the single most technically sophisticated component of the entire solution—and the decisive dividing line between ‘mass-producible technology’ and ‘paper-only research’. The result: a 53.5% increase in transistor density, a core clock frequency of 3.1 GHz, and a 41% improvement in P-core energy efficiency. The five-year target is ‘1.4-nanometer equivalent’ performance. Note a critical detail: these metrics do not depend on more advanced EUV lithography equipment. II. Why Moore’s Law is dead—and the cost of engineering path dependence This is a question debated for decades, yet rarely confronted head-on. At its core, Moore’s Law rests on ‘geometric scaling’—the continual reduction of transistor physical dimensions. When Gordon Moore first proposed this observation in 1965, transistor feature sizes were measured in micrometers. Today, they’ve shrunk to the nanometer scale—down to atomic spacing levels: the diameter of a silicon atom is merely 0.22 nanometers, and transistor channels span only a dozen atoms wide. To shrink further would mean compressing features into the gaps *between* atoms. When quantum mechanics delivers its iron-fisted verdict, it brooks no argument. Yet the entire industry took over a decade to accept this reality. Why? Because path dependence is the most formidable inertia in engineering. For the past six decades, every semiconductor company’s R&D system, talent structure, equipment investment, and technology roadmap has been built entirely upon the trajectory of ‘process node scaling’.

Morning Bid: China Chip Champion

Jul 27, 2026

China's CXMT soared nearly 500% on its Shanghai IPO debut, overtaking ICBC as the nation's most valuable stock, while Brent crude oil prices retreated below $90/barrel amid geopolitical easing.

reuters

Morning Bid: China Chip Champion

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